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Fix links

Jordi Pakey-Rodriguez 2018-01-02 13:07:54 -06:00
parent 6be0de08f7
commit 79fa1e9f2d
1 changed files with 7 additions and 7 deletions
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14
Instruction-Set.md

@ -173,7 +173,7 @@ destination = destination & source
destination = destination | source destination = destination | source
``` ```
### SHL (Shift Logical Left) ### SHL
#### Details #### Details
| mnemonic | opcode | operands | carry | zero | sign | overflow | break | | mnemonic | opcode | operands | carry | zero | sign | overflow | break |
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- | | -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
@ -181,7 +181,7 @@ destination = destination | source
| | | `count` : `reg` / `mem` / `imm` | | | | `count` : `reg` / `mem` / `imm` |
#### Description #### Description
`SHL` shifts the bits of the destination operand upward (toward the `SHL` (Shift Logical Left) shifts the bits of the destination operand upward (toward the
most significant bit) by the number of bit positions specified in most significant bit) by the number of bit positions specified in
the second operand (`count`). As bits are transferred out of the the second operand (`count`). As bits are transferred out of the
left (high-order) end of the destination, zero bits are shifted left (high-order) end of the destination, zero bits are shifted
@ -194,7 +194,7 @@ The carry flag (CF) is set equal to the last bit shifted out of the left end.
destination = destination << count destination = destination << count
``` ```
### SHR (Shift Logical Right) ### SHR
#### Details #### Details
| mnemonic | opcode | operands | carry | zero | sign | overflow | break | | mnemonic | opcode | operands | carry | zero | sign | overflow | break |
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- | | -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
@ -202,9 +202,9 @@ destination = destination << count
| | | `count` : `reg` / `mem` / `imm` | | | | `count` : `reg` / `mem` / `imm` |
#### Description #### Description
SHR shifts the bits of the destination operand downward (toward `SHR` (Shift Logical Right) shifts the bits of the destination operand downward (toward
the least significant bit) by the number of bit positions the least significant bit) by the number of bit positions
specified in the second operand (count). As bits are transferred specified in the second operand (`count`). As bits are transferred
out of the right (low-order) end of the destination, zero bits are out of the right (low-order) end of the destination, zero bits are
shifted into the left (high-order) end. shifted into the left (high-order) end.
@ -213,14 +213,14 @@ SHR shifts the bits of the destination operand downward (toward
destination = destination >> count destination = destination >> count
``` ```
### HWI (Hardware Interrupt) ### HWI
#### Details #### Details
| mnemonic | opcode | operands | carry | zero | sign | overflow | break | | mnemonic | opcode | operands | carry | zero | sign | overflow | break |
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- | | -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
| `HWI source` | `0x09` | `source` : `reg` / `mem` / `imm` | `-` | `-` | `-` | `-` | `-` | | `HWI source` | `0x09` | `source` : `reg` / `mem` / `imm` | `-` | `-` | `-` | `-` | `-` |
#### Description #### Description
`HWI` triggers an [Hardware Interrupt](https://github.com/simon987/Much-Assembly-Required/wiki/Hardware). `source` should be the address of the harware device. This is differnt from the RAM memory addresses. See the documentation of the hardware devices to see what an `HWI` does for each device. `HWI` triggers a [Hardware Interrupt](https://github.com/simon987/Much-Assembly-Required/wiki/Hardware). `source` should be the address of the harware device. This is differnt from the RAM memory addresses. See the documentation of the hardware devices to see what an `HWI` does for each device.
### JMP ### JMP
#### Details #### Details