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Added first bit of the SAR instruction

Kevin Ramharak 2018-02-04 09:12:05 +01:00
parent 2525d38b7e
commit f29e926b4a
1 changed files with 25 additions and 1 deletions
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26
Instruction-Set.md

@ -202,6 +202,7 @@ The carry flag (CF) is set equal to the last bit shifted out of the left end.
#### Pseudo code #### Pseudo code
```py ```py
destination = destination << count destination = destination << count
#NOTE: be aware of the difference between a logical and an arithmetic shift
``` ```
### SHR ### SHR
@ -221,6 +222,7 @@ destination = destination << count
#### Pseudo code #### Pseudo code
```py ```py
destination = destination >> count destination = destination >> count
#NOTE: be aware of the difference between a logical and an arithmetic shift
``` ```
### HWI ### HWI
@ -827,7 +829,7 @@ if count == 1:
| mnemonic | opcode | operands | carry | zero | sign | overflow | break | | mnemonic | opcode | operands | carry | zero | sign | overflow | break |
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- | | -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
| `RCR destination, count` | `0x28` | `destination` : `mem` / `reg` | `X` | `-` | `-` | `X` | `-` | | `RCR destination, count` | `0x28` | `destination` : `mem` / `reg` | `X` | `-` | `-` | `X` | `-` |
| | | `count` : `mem` / `reg`, `imm` | | | | `count` : `mem` / `reg` / `imm` |
#### Description #### Description
`RCR` shifts the bits of the `destination` operand to the right by the `RCR` shifts the bits of the `destination` operand to the right by the
@ -867,6 +869,27 @@ if count == 1:
OVERFLOW_FLAG = (old_sign_bit != new_sign_bit) OVERFLOW_FLAG = (old_sign_bit != new_sign_bit)
``` ```
### SAR
#### Details
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
| `SAR destination, count` | `0x29` | `destination` : `mem` / `reg` | `X` | `X` | `X` | `X` | `-` |
| | | `count` : `mem` / `reg`/ `imm` |
#### Description
The `SAR` (Shift Arithmetic Right) instruction shifts the bits of the destination operand downward (toward the least significant bit) by the number of bit positions specified in the second operand (count).
As bits are transferred out of the right (low-order) end of the destination, bits equal to the original sign bit are shifted into the left (high-order) end, thereby preserving the sign bit. The carry flag (CF) is set equal to the last bit shifted out of the right end.
If the count operand is not an immediate 1, the overflow flag (OF) is undefined; otherwise SAR resets OF to zero.
> TODO: Not sure if this part is implemented, should check source code
> TODO: Plain english? (now copy pasta from the [manual](http://www.ousob.com/ng/iapx86/ng215f0.php))
### Pseudo code
```py
destination = destination <<< count
#NOTE: be aware of the difference between a logical and an arithmetic shift
```
### INC ### INC
#### Details #### Details
| mnemonic | opcode | operands | carry | zero | sign | overflow | break | | mnemonic | opcode | operands | carry | zero | sign | overflow | break |
@ -879,6 +902,7 @@ if count == 1:
```py ```py
destination = destination + 1 destination = destination + 1
``` ```
### DEC ### DEC
#### Details #### Details
| mnemonic | opcode | operands | carry | zero | sign | overflow | break | | mnemonic | opcode | operands | carry | zero | sign | overflow | break |