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moved stuff + added flags clarification

Kevin Ramharak 2018-01-02 13:19:01 +01:00
parent 3b72b5f9c0
commit 393a9d165d
1 changed files with 31 additions and 22 deletions
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Instruction-Set.md

@ -44,27 +44,8 @@
| [**XCHG**](#cxhg) *destination*, *source* | *mem/reg*, *mem/reg* | 0x1F |`- - - - -` | | [**XCHG**](#cxhg) *destination*, *source* | *mem/reg*, *mem/reg* | 0x1F |`- - - - -` |
| [**XOR**](#xor) *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x26 |`0 X X 0 -` | | [**XOR**](#xor) *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x26 |`0 X X 0 -` |
### Instruction encoding
Instructions are 1-3 words long and are fully defined by the first word.
In a basic instruction, the lower 6 bits of the first word of the instruction
are the opcode, and the remaining 10 bits are split into a 5 bit destination operand
and a 5 bit source operand.
In bits, a basic instruction has the format: `sssssdddddoooooo`
Operand value:
| Description | Value |
| --- | --- |
| Invalid or none | `00000` |
| Immediate value at IP+1 | `11111` |
| [Immediate value at IP+1] | `11110` |
| Register | `00001`-`01000` |
| [Register] | `01001`-`10000` |
| Register + Immediate value at IP+1 | `10001`-`11000` |
*** ***
> NOTE: Work In Progress
# Instruction Set # Instruction Set
## Introduction ## Introduction
This is an effort to specify the specific MAR Assembly Instruction Set and its behaviour. The instruction set is a subset of the 8086 instruction set. A more detailed specification if the 8086 Instruction Set can be found [here](http://www.ousob.com/ng/iapx86/ng2e5.php). Note that the MAR Instruction Set can differ from the 8086 Instruction Set. This is an effort to specify the specific MAR Assembly Instruction Set and its behaviour. The instruction set is a subset of the 8086 instruction set. A more detailed specification if the 8086 Instruction Set can be found [here](http://www.ousob.com/ng/iapx86/ng2e5.php). Note that the MAR Instruction Set can differ from the 8086 Instruction Set.
@ -77,7 +58,7 @@ Each instruction has a `Mnemonic` or syntax. This is the way the instruction is
MOV A, 0x20 MOV A, 0x20
``` ```
This human readable format is parsed by the assembler which will output the actual binary opcodes and operands. More about the encoding can be read [below](#Encoding). This human readable format is parsed by the assembler which will output the actual binary opcodes and operands.
## Flags ## Flags
Some instructions will change certain flags based on their result. These are in a special non read-write register. Some instructions will change certain flags based on their result. These are in a special non read-write register.
@ -85,7 +66,17 @@ The only way to set these flags is by using instructions and the only way to rea
> NOTE: The flags might be readable in the future > NOTE: The flags might be readable in the future
for more information check the [docs](https://github.com/simon987/Much-Assembly-Required/wiki/CPU#the-flags-register) >for more information check the [docs](https://github.com/simon987/Much-Assembly-Required/wiki/CPU#the-flags-register)
> NOTE: The table below was copied from the link above. There is more info available, if you have trouble understanding the flags we strongly suggest you read the section in the link.
| Flag | Description |
|:--------- |:----------- |
| **CF** (Carry flag) | Relevant for *unsigned* operations. Indicates that there was a carry out of the most significant (leftmost) bit |
| **ZF** (Zero flag) | Indicates that the result of an operation is 0 |
| **SF** (Sign flag) | Indicates that the most significant (leftmost) bit of the result of an operation is set |
| **OF** (Overflow flag) | Relevant for *signed* operations. Indicates that the sign of the result of an signed operation is wrong (See examples below) |
| **BF** (Break flag) | Tells the CPU to stop the execution. This flag is set with the **BRK** instruction. |
#### ####
@ -878,3 +869,21 @@ if count == 1:
```py ```py
# do nothing # do nothing
``` ```
### Instruction encoding
Instructions are 1-3 words long and are fully defined by the first word.
In a basic instruction, the lower 6 bits of the first word of the instruction
are the opcode, and the remaining 10 bits are split into a 5 bit destination operand
and a 5 bit source operand.
In bits, a basic instruction has the format: `sssssdddddoooooo`
Operand value:
| Description | Value |
| --- | --- |
| Invalid or none | `00000` |
| Immediate value at IP+1 | `11111` |
| [Immediate value at IP+1] | `11110` |
| Register | `00001`-`01000` |
| [Register] | `01001`-`10000` |
| Register + Immediate value at IP+1 | `10001`-`11000` |