mirror of
https://github.com/simon987/Much-Assembly-Required.git
synced 2025-04-18 02:06:43 +00:00
added missing instructions. Also changed NEG to in the table to avoid confusion
Kevin Ramharak
parent
eb0e02f4ac
commit
226529e3fb
@ -3,48 +3,46 @@
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### Instruction table with affected flags
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| Instruction mnemonic | Operands | Opcode | `C Z S O B` |
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| -------------------- |:-------- |:------:|:--------- |
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| **ADD** *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x02 | `X X X X -` |
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| **AND** *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x04 | `0 X X 0 -` |
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| **BRK** | *None* | 0x00 |`- - - - 1` |
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| **CALL** *target* | *mem/reg/imm* | 0x15 |`- - - - -` |
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| **CMP** *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x0C |`X X X X -` |
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| **DIV** *source* | *mem/reg/imm* | 0x18 |`- - - - -` |
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| **HWI** *source* | *mem/reg/imm* | 0x09 |`- - - - -` |
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| **HWQ** *source* | *mem/reg/imm* | 0x1C |`- - - - -` |
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| **JC** *target* | *mem/reg/imm* | 0x21 |`- - - - -` |
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| **JG** *target* | *mem/reg/imm* | 0x0F |`- - - - -` |
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| **JGE** *target* | *mem/reg/imm* | 0x10 |`- - - - -` |
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| **JL** *target* | *mem/reg/imm* | 0x11 |`- - - - -` |
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| **JLE** *target* | *mem/reg/imm* | 0x12 |`- - - - -` |
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| **JMP** *target* | *mem/reg/imm* | 0x0A |`- - - - -` |
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| **JNC** *target* | *mem/reg/imm* | 0x22 |`- - - - -` |
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| **JNO** *target* | *mem/reg/imm* | 0x25 |`- - - - -` |
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| **JNS** *target* | *mem/reg/imm* | 0x1B |`- - - - -` |
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| **JNZ** *target* | *mem/reg/imm* | 0x0D |`- - - - -` |
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| **JO** *target* | *mem/reg/imm* | 0x24 |`- - - - -` |
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| **JS** *target* | *mem/reg/imm* | 0x1A |`- - - - -` |
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| **JZ** *target* | *mem/reg/imm* | 0x0E |`- - - - -` |
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| **MOV** *destination*, *source* | *mem/reg*, *mem/reg/imm* |0x01 |`- - - - -` |
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| **MUL** *source* | *mem/reg/imm* | 0x17 |`X - - X -` |
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| **NEG** *destination* | *mem/reg* | 0x19 |`1 X X X -`* |
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| **NOP** | *None* | 0x3F |`- - - - -` |
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| **NOT** *destination* | *mem/reg* | 0x1D |`- - - - -` |
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| **OR** *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x05 |`0 X X 0 -` |
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| **POP** *destination* | *mem/reg* | 0x14 |`- - - - -` |
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| **PUSH** *source* | *mem/reg/imm* | 0x13 |`- - - - -` |
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| **RCL** *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x27 |`X - - X -` |
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| **RCR** *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x28 |`X - - X -` |
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| **RET** *optional-pop-value* | *imm/None* | 0x16 |`- - - - -` |
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| **ROL** *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x23 |`X - - X -` |
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| **ROR** *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x20 |`X - - X -` |
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| **SHL** *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x06 |`X - - X -` |
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| **SHR** *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x07 |`X - - X -` |
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| **SUB** *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x03 |`X X X X -` |
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| **TEST** *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x0B |`0 X X 0 -` |
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| **XCHG** *destination*, *source* | *mem/reg*, *mem/reg* | 0x1F |`- - - - -` |
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| **XOR** *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x26 |`0 X X 0 -` |
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*NEG instruction: CF is set to 0 if destination=0
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| [**ADD**](#ADD) *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x02 | `X X X X -` |
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| [**AND**](#AND) *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x04 | `0 X X 0 -` |
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| [**BRK**](#BRK) | *None* | 0x00 |`- - - - 1` |
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| [**CALL**](#CALL) *target* | *mem/reg/imm* | 0x15 |`- - - - -` |
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| [**CMP**](#CMP) *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x0C |`X X X X -` |
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| [**DIV**](#DIV) *source* | *mem/reg/imm* | 0x18 |`- - - - -` |
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| [**HWI**](#HWI) *source* | *mem/reg/imm* | 0x09 |`- - - - -` |
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| [**HWQ**](#HWQ) *source* | *mem/reg/imm* | 0x1C |`- - - - -` |
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| [**JC**](#JC) *target* | *mem/reg/imm* | 0x21 |`- - - - -` |
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| [**JG**](#JG) *target* | *mem/reg/imm* | 0x0F |`- - - - -` |
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| [**JGE**](#JGE) *target* | *mem/reg/imm* | 0x10 |`- - - - -` |
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| [**JL**](#JL) *target* | *mem/reg/imm* | 0x11 |`- - - - -` |
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| [**JLE**](#JLE) *target* | *mem/reg/imm* | 0x12 |`- - - - -` |
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| [**JMP**](#JMP) *target* | *mem/reg/imm* | 0x0A |`- - - - -` |
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| [**JNC**](#JNC) *target* | *mem/reg/imm* | 0x22 |`- - - - -` |
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| [**JNO**](#JNO) *target* | *mem/reg/imm* | 0x25 |`- - - - -` |
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| [**JNS**](#JNS) *target* | *mem/reg/imm* | 0x1B |`- - - - -` |
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| [**JNZ**](#JNZ) *target* | *mem/reg/imm* | 0x0D |`- - - - -` |
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| [**JO**](#JO) *target* | *mem/reg/imm* | 0x24 |`- - - - -` |
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| [**JS**](#JS) *target* | *mem/reg/imm* | 0x1A |`- - - - -` |
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| [**JZ**](#JZ) *target* | *mem/reg/imm* | 0x0E |`- - - - -` |
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| [**MOV**](#MOV) *destination*, *source* | *mem/reg*, *mem/reg/imm* |0x01 |`- - - - -` |
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| [**MUL**](#MUL) *source* | *mem/reg/imm* | 0x17 |`X - - X -` |
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| [**NEG**](#NEG) *destination* | *mem/reg* | 0x19 |`X X X X -`* |
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| [**NOP**](#NOP) | *None* | 0x3F |`- - - - -` |
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| [**NOT**](#NOT) *destination* | *mem/reg* | 0x1D |`- - - - -` |
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| [**OR**](#OR) *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x05 |`0 X X 0 -` |
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| [**POP**](#POP) *destination* | *mem/reg* | 0x14 |`- - - - -` |
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| [**PUSH**](#PUSH) *source* | *mem/reg/imm* | 0x13 |`- - - - -` |
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| [**RCL**](#RCL) *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x27 |`X - - X -` |
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| [**RCR**](#RCR) *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x28 |`X - - X -` |
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| [**RET**](#RET) *optional-pop-value* | *imm/None* | 0x16 |`- - - - -` |
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| [**ROL**](#ROL) *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x23 |`X - - X -` |
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| [**ROR**](#ROR) *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x20 |`X - - X -` |
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| [**SHL**](#SHL) *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x06 |`X - - X -` |
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| [**SHR**](#SHR) *destination*, *count* | *mem/reg*, *mem/reg/imm* | 0x07 |`X - - X -` |
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| [**SUB**](#SUB) *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x03 |`X X X X -` |
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| [**TEST**](#TEST) *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x0B |`0 X X 0 -` |
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| [**XCHG**](#XCHG) *destination*, *source* | *mem/reg*, *mem/reg* | 0x1F |`- - - - -` |
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| [**XOR**](#XOR) *destination*, *source* | *mem/reg*, *mem/reg/imm* | 0x26 |`0 X X 0 -` |
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### Instruction encoding
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Instructions are 1-3 words long and are fully defined by the first word.
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@ -53,13 +51,13 @@ are the opcode, and the remaining 10 bits are split into a 5 bit destination ope
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and a 5 bit source operand.
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In bits, a basic instruction has the format: `sssssdddddoooooo`
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Operand value:
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Operand value:
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| Description | Value |
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| --- | --- |
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| Invalid or none | `00000` |
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| Immediate value at IP+1 | `11111` |
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| [Immediate value at IP+1] | `11110` |
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| Description | Value |
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| --- | --- |
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| Invalid or none | `00000` |
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| Immediate value at IP+1 | `11111` |
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| [Immediate value at IP+1] | `11110` |
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| Register | `00001`-`01000` |
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| [Register] | `01001`-`10000` |
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| Register + Immediate value at IP+1 | `10001`-`11000` |
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@ -81,7 +79,18 @@ MOV A, 0x20
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This human readable format is parsed by the assembler which will output the actual binary opcodes and operands. More about the encoding can be read [below](#Encoding).
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## Flags
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Some instructions will change certain flags based on their result. These are in a special non read-write register.
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The only way to set these flags is by using instructions and the only way to read these flags is with the jump behaviour
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> NOTE: The flags might be readable in the future
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for more information check the [docs](https://github.com/simon987/Much-Assembly-Required/wiki/CPU#the-flags-register)
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####
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## Instructions
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### BRK
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#### Details
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| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
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@ -118,7 +127,7 @@ destination = source
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### Pseudo code
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```py
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destination = destination + source
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result = destination + source
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```
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### SUB
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@ -131,9 +140,6 @@ destination = destination + source
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#### Description
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`SUB` subtracts the source operand from the destination operand and stores the result in destination.
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> ? TODO: is this implemented?
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> When an immediate byte value is subtracted from a word operand, the immediate value is first sign-extended to the size of the destination operand.
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#### Pseudo code
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```py
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destination = destination - source
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@ -179,19 +185,17 @@ destination = destination | source
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#### Details
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| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
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| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
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| `SHL destination, count` | `0x06` | `destination` : `reg` / `mem` | `X` | `-` | `-` | `X` | `-` |
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| `SHL destination, count` | `0x06` | `destination` : `reg` / `mem` | `X` | `X` | `X` | `X` | `-` |
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| | | `count` : `reg` / `mem` / `imm` |
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#### Description
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`SHL` shifts the bits of the destination operand upward (toward the
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most significant bit) by the number of bit positions specified in
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the second operand (count). As bits are transferred out of the
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the second operand (`count`). As bits are transferred out of the
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left (high-order) end of the destination, zero bits are shifted
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into the right (low-order) end.
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> ? TODO: is this implemented?
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> The carry flag (CF) is set equal
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to the last bit shifted out of the left end.
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The carry flag (CF) is set equal to the last bit shifted out of the left end.
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#### Pseudo code
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```py
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@ -212,10 +216,6 @@ SHR shifts the bits of the destination operand downward (toward
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out of the right (low-order) end of the destination, zero bits are
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shifted into the left (high-order) end.
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> ? TODO: is this implemented?
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> The carry flag (CF) is set
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equal to the last bit shifted out of the right end.
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#### Pseudo code
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```py
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destination = destination >> count
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@ -272,10 +272,6 @@ destination & source # flags will be set
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destination and updates the flags. None of the operands are
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changed.
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> ? TODO: is this implemented correctly?
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> I see differing results using test/jz vs cmp/jnz that seem to involve overflow from the latter?
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#### Pseudo code
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```py
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destination - source # flags will be set
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@ -452,13 +448,12 @@ The result of the multiplication is stored into `Y:A` where the higher order bit
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The carry and overflow flags are set to 1 if the high-order of the result is bigger than 0; otherwise, CF and OF are reset to 0.
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> This is a somewhat complicated instruction
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> See the [source](https://github.com/simon987/Much-Assembly-Required/blob/master/Server/source/main/java/net/simon987/server/assembly/instruction/MulInstruction.java) if needed
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> This is a somewhat complicated instruction,
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> see the [source](https://github.com/simon987/Much-Assembly-Required/blob/master/Server/source/main/java/net/simon987/server/assembly/instruction/MulInstruction.java) if needed
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#### Pseudo code
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```py
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# result is a 32-bit integer
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result = A * source
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# get the 16 most significant bits of result
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@ -486,12 +481,12 @@ A = (result & 0x00ff)
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#### Description
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`DIV` performs unsigned division on `Y:A` with `source` as divisor and stores the result into `A` and the remainder in `Y`.
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> NOTE: `DIV` operates on a 32 bit integer composed of `Y:A`. So multiple `DIV` instructions without setting Y to what you want will result into weird results
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> NOTE: `DIV` operates on a 32 bit integer composed of `Y:A`. So multiple `DIV` instructions without setting Y to what you want will result into unexpected results
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Note that a division by 0 will set the (undocumented) error flag and the break flag. This will halt execution.
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> NOTE: that a division by 0 will set the (undocumented) error flag and the break flag. This will halt execution.
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> This is a somewhat complicated instruction
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> See the [source](https://github.com/simon987/Much-Assembly-Required/blob/master/Server/source/main/java/net/simon987/server/assembly/instruction/DivInstruction.java) if needed
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> This is a somewhat complicated instruction,
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> see the [source](https://github.com/simon987/Much-Assembly-Required/blob/master/Server/source/main/java/net/simon987/server/assembly/instruction/DivInstruction.java) if needed
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#### Pseudo code
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@ -516,7 +511,7 @@ Y = temp % source
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| `NEG destintation` | `0x19` | `destination` : `mem` / `reg` | `X` | `X` | `X` | `X` | `-` |
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#### Description
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`NEG` subtracts the destination operand from 0 and returns the result in the destination. This effectively produces the two's complement of the operand.
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`NEG` subtracts the `destination` operand from 0 and returns the result in the `destination`. This effectively produces the two's complement of the operand.
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If the operand is zero, the carry flag is cleared; in all other cases, the carry flag is set.
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@ -543,7 +538,7 @@ else
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| `JS target` | `0x1A` | `target` : `mem` / `reg` / `imm` | `-` | `-` | `-` | `-` | `-` |
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#### Description
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`JS` jumps to the target if the sign flag **IS** set.
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`JS` jumps to the `target` if the sign flag **IS** set.
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#### Pseudo code
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```py
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@ -558,7 +553,7 @@ if SIGN_FLAG == 1:
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| `JNS target` | `0x1B` | `target` : `mem` / `reg` / `imm` | `-` | `-` | `-` | `-` | `-` |
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#### Description
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`JNS` jumps to the target if the sign flag **IS NOT** set.
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`JNS` jumps to the `target` if the sign flag **IS NOT** set.
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#### Pseudo code
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```py
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@ -578,7 +573,10 @@ if SIGN_FLAG == 0:
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#### Pseudo code
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```py
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if hardware_memory[source] != None:
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B = get_hardware_id(hardware_memory[source]) # not sure how to (pseudo) code this
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# not sure how to (pseudo) code this
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B = get_hardware_id(
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hardware_memory[source]
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)
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else:
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B = 0
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```
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@ -587,7 +585,7 @@ else:
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#### Details
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| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
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| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
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| `NOT destintation` | `0x1D` | `source` : `mem` / `reg` | `-` | `-` | `-` | `-` | `-` |
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| `NOT destination` | `0x1D` | `source` : `mem` / `reg` | `-` | `-` | `-` | `-` | `-` |
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#### Description
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`NOT` inverts each bit in its operand, i.e. forms the one's complement.
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@ -597,4 +595,287 @@ else:
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dest = ~dest
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```
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## Encoding
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### XCHG
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#### Details
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| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
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| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
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| `XCHG destination, source` | `0x1F` | `destination` : `mem` / `reg` | `-` | `-` | `-` | `-` | `-` |
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| | | `source` : `mem` / `reg` |
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#### Description
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`XCHG` switches the contents of two operands.
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#### Pseudo code
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```py
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temp = destination
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destination = source
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source = destination
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```
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### ROR
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| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
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| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
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| `ROR destination, count` | `0x20` | `destination` : `mem` / `reg` | `X` | `-` | `-` | `X` | `-` |
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| | | `count` : `mem` / `reg`, `imm` |
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#### Description
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`ROR` shifts the bits of `destination` operand to the right by the number of bit positions specified by `count`.
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if `count` is greater than 15 it will be the remainder of a division by 16.
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as bits are transferred out the right (low-order) end of the destination, they re-enter on the left (high-order) end. The carry flag (CF) is updated to match the last bit shifted out of the right end.
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if `count` equals 1 then the overflow flag will be set if the sign bit of `destination` has changed
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#### Pseudo code
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```py
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count = count % 16
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# TODO: less implementation more pseudo code
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if (destination & 0x8000) > 0: # check if sign bit was set
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old_sign_bit = 1
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else
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old_sign_bit = 0
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destination = #... ROR magic
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|
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if (destination & 0x8000) > 0: # check if sign bit was set
|
||||
new_sign_bit = 1
|
||||
else
|
||||
new_sign_bit = 0
|
||||
|
||||
if count == 1:
|
||||
OVERFLOW_FLAG = (old_signbit == new_signbit) # check if sign bit changed
|
||||
|
||||
if new_sign_bit == 1:
|
||||
CARRY_FLAG = 1
|
||||
else:
|
||||
CARRY_FLAG = 1
|
||||
```
|
||||
|
||||
# JC
|
||||
#### Details
|
||||
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
|
||||
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
|
||||
| `JC target` | `0x21` | `target` : `mem` / `reg` / `imm` | `-` | `-` | `-` | `-` | `-` |
|
||||
|
||||
#### Description
|
||||
`JC` jumps to the `target` if the carry flag **IS** set.
|
||||
|
||||
#### Pseudo code
|
||||
```py
|
||||
if CARRY_FLAG == 1:
|
||||
IP = target
|
||||
```
|
||||
|
||||
# JNC
|
||||
#### Details
|
||||
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
|
||||
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
|
||||
| `JNC target` | `0x22` | `target` : `mem` / `reg` / `imm` | `-` | `-` | `-` | `-` | `-` |
|
||||
|
||||
#### Description
|
||||
`JNC` jumps to the `target` if the carry flag **IS NOT** set.
|
||||
|
||||
#### Pseudo code
|
||||
```py
|
||||
if CARRY_FLAG == 0:
|
||||
IP = target
|
||||
```
|
||||
|
||||
### ROL
|
||||
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
|
||||
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
|
||||
| `ROL destination, count` | `0x23` | `destination` : `mem` / `reg` | `X` | `-` | `-` | `X` | `-` |
|
||||
| | | `count` : `mem` / `reg`, `imm` |
|
||||
|
||||
#### Description
|
||||
`ROL` shifts the bits of `destination` operand to the left by the number of bit positions specified by `count`.
|
||||
|
||||
if `count` is greater than 15 it will be the remainder of a division by 16.
|
||||
|
||||
as bits are transferred out the left (high-order) end of the destination, they re-enter on the right (low-order) end. The carry flag (CF) is updated to match the last bit shifted out of the left end.
|
||||
|
||||
if `count` equals 1 then the overflow flag will be set if the sign bit of `destination` has changed
|
||||
|
||||
#### Pseudo code
|
||||
```py
|
||||
count = count % 16
|
||||
|
||||
# TODO: less implementation more pseudo code
|
||||
if (destination & 0x8000) > 0: # check if sign bit was set
|
||||
old_sign_bit = 1
|
||||
else
|
||||
old_sign_bit = 0
|
||||
|
||||
destination = #... ROL magic
|
||||
|
||||
# carry flag might be set
|
||||
|
||||
if (destination & 0x8000) > 0: # check if sign bit was set
|
||||
new_sign_bit = 1
|
||||
else
|
||||
new_sign_bit = 0
|
||||
|
||||
if count == 1:
|
||||
OVERFLOW_FLAG = (old_signbit == new_signbit) # check if sign bit changed
|
||||
|
||||
# TODO: less implementation more pseudo code
|
||||
if (destination & 0x01) == 1:
|
||||
CARRY_FLAG = 1
|
||||
else:
|
||||
CARRY_FLAG = 1
|
||||
```
|
||||
|
||||
# JO
|
||||
#### Details
|
||||
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
|
||||
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
|
||||
| `JO target` | `0x24` | `target` : `mem` / `reg` / `imm` | `-` | `-` | `-` | `-` | `-` |
|
||||
|
||||
#### Description
|
||||
`JO` jumps to the `target` if the overflow flag **IS** set.
|
||||
|
||||
#### Pseudo code
|
||||
```py
|
||||
if OVERFLOW_FLAG == 1:
|
||||
IP = target
|
||||
```
|
||||
|
||||
# JNO
|
||||
#### Details
|
||||
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
|
||||
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
|
||||
| `JNO target` | `0x25` | `target` : `mem` / `reg` / `imm` | `-` | `-` | `-` | `-` | `-` |
|
||||
|
||||
#### Description
|
||||
`JNO` jumps to the `target` if the overflow flag **IS NOT** set.
|
||||
|
||||
#### Pseudo code
|
||||
```py
|
||||
if OVERFLOW_FLAG == 0:
|
||||
IP = target
|
||||
```
|
||||
|
||||
XOR destination, source mem/reg, mem/reg/imm 0x26 0 X X 0 -
|
||||
### XOR
|
||||
#### Details
|
||||
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
|
||||
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
|
||||
| `XOR destination, source` | `0x26` | `destination` : `reg` / `mem` | `0` | `X` | `X` | `0` | `-` |
|
||||
| | | `source` : `reg` / `mem` / `imm` |
|
||||
|
||||
#### Description
|
||||
XOR performs a bit-by-bit "exclusive or" on its two operands, and
|
||||
returns the result in the destination operand. XOR sets each bit
|
||||
of the result to one if only one of the corresponding bits is set
|
||||
to one.
|
||||
|
||||
#### Pseudo code
|
||||
```py
|
||||
destination = destination ^ source
|
||||
```
|
||||
|
||||
### RCL
|
||||
#### Details
|
||||
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
|
||||
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
|
||||
| `RCL destination, count` | `0x27` | `destination` : `mem` / `reg` | `X` | `-` | `-` | `X` | `-` |
|
||||
| | | `count` : `mem` / `reg`, `imm` |
|
||||
|
||||
#### Description
|
||||
`RCL` shifts the bits of the `destination` operand to the left by the
|
||||
number of bit positions specified in the count operand. A bit
|
||||
shifted out of the left (high-order) end of the destination enters
|
||||
the carry flag (CF), and the displaced carry flag rotates around
|
||||
to enter the vacated right-most bit position of the destination.
|
||||
Another way of looking at this is to consider the carry flag as
|
||||
the highest order bit of the word being rotated.
|
||||
|
||||
if `count` is bigger than 16 it will be the remainder of a division by 17.
|
||||
|
||||
The shift is repeated the number of times indicated by the `count` operand
|
||||
|
||||
if `count` equals 1 then the overflow flag will be set if the sign bit of `destination` has changed
|
||||
|
||||
#### Pseudo code
|
||||
```py
|
||||
count = count % 17
|
||||
|
||||
# TODO: less implementation more pseudo code
|
||||
if (destination & 0x8000) > 0:
|
||||
old_sign_bit = 1
|
||||
else
|
||||
old_sign_bit = 0
|
||||
|
||||
destination = # ... RCL magic
|
||||
|
||||
# carry flag might be set
|
||||
|
||||
if (destination & 0x8000) > 0:
|
||||
new_sign_bit = 1
|
||||
else:
|
||||
new_sign_bit = 0
|
||||
|
||||
if count == 1:
|
||||
OVERFLOW_FLAG = old_sign_bit == new_sign_bit)
|
||||
```
|
||||
|
||||
### RCR
|
||||
#### Details
|
||||
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
|
||||
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
|
||||
| `RCR destination, count` | `0x28` | `destination` : `mem` / `reg` | `X` | `-` | `-` | `X` | `-` |
|
||||
| | | `count` : `mem` / `reg`, `imm` |
|
||||
|
||||
#### Description
|
||||
`RCR` shifts the bits of the `destination` operand to the right by the
|
||||
number of bit positions specified in the `count` operand. A bit
|
||||
shifted out of the right (low-order) end of the destination enters
|
||||
the carry flag (CF), and the displaced carry flag rotates around
|
||||
to enter the vacated left-most bit position of the destination.
|
||||
Another way of looking at this is to consider the carry flag as
|
||||
the lowest order bit of the word being rotated.
|
||||
|
||||
if `count` is bigger than 16 it will be the remainder of a division by 17.
|
||||
|
||||
The shift is repeated the number of times indicated by the `count` operand
|
||||
|
||||
if `count` equals 1 then the overflow flag will be set if the sign bit of `destination` has changed
|
||||
|
||||
#### Pseudo code
|
||||
```py
|
||||
count = count % 17
|
||||
|
||||
# TODO: less implementation more pseudo code
|
||||
if (destination & 0x8000) > 0:
|
||||
old_sign_bit = 1
|
||||
else
|
||||
old_sign_bit = 0
|
||||
|
||||
destination = # ... RCL magic
|
||||
|
||||
# carry flag might be set
|
||||
|
||||
if (destination & 0x8000) > 0:
|
||||
new_sign_bit = 1
|
||||
else:
|
||||
new_sign_bit = 0
|
||||
|
||||
if count == 1:
|
||||
OVERFLOW_FLAG = old_sign_bit == new_sign_bit)
|
||||
```
|
||||
|
||||
### NOP
|
||||
#### Details
|
||||
| mnemonic | opcode | operands | carry | zero | sign | overflow | break |
|
||||
| -------- | ------ | -------- | ----- | ---- | ---- | -------- | ----- |
|
||||
| `NOP` | `0x3F` | | `-` | `-` | `-` | `-` | `-` |
|
||||
|
||||
### Description
|
||||
`NOP` is an instruction that performs no operation. Often used for timing purposes, as a placeholder or for aligning purposes.
|
||||
|
||||
### Pseudo code
|
||||
```py
|
||||
# do nothing
|
||||
```
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user