Bug fixes for various operands

This commit is contained in:
simon 2017-11-18 22:21:14 -05:00
parent e09d2c1b16
commit d004386b7b

View File

@ -282,7 +282,7 @@ public class CPU implements JSONSerialisable{
if (destination == 0) { if (destination == 0) {
//Single operand //Single operand
ip++; ip++;
instruction.execute(memory, registerSet.get(source), status); instruction.execute(memory, registerSet.get(source - registerSetSize), status);
} else if (destination == Operand.IMMEDIATE_VALUE) { } else if (destination == Operand.IMMEDIATE_VALUE) {
//Destination is an immediate value //Destination is an immediate value
//this shouldn't happen //this shouldn't happen
@ -299,7 +299,7 @@ public class CPU implements JSONSerialisable{
} else if (destination <= registerSetSize * 2) { } else if (destination <= registerSetSize * 2) {
//Destination is [reg] //Destination is [reg]
ip++; ip++;
instruction.execute(memory, registerSet.get(destination - registerSetSize), memory, registerSet.get(source), status); instruction.execute(memory, registerSet.get(destination - registerSetSize), memory, registerSet.get(source - registerSetSize), status);
} else { } else {
//Assuming that destination is [reg + x] //Assuming that destination is [reg + x]
ip += 2; ip += 2;
@ -327,7 +327,7 @@ public class CPU implements JSONSerialisable{
ip += 2; ip += 2;
instruction.execute(memory, memory.get(ip - 1), memory, instruction.execute(memory, memory.get(ip - 1), memory,
registerSet.get(source - registerSetSize - registerSetSize) + sourceDisp, status); registerSet.get(source - registerSetSize - registerSetSize) + sourceDisp, status);
} else if (destination < registerSetSize) { } else if (destination <= registerSetSize) {
//Destination is a register //Destination is a register
ip++; ip++;
instruction.execute(registerSet, destination, memory, instruction.execute(registerSet, destination, memory,